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INTEGRATED CIRCUITS
DATA SHEET
74LVT32374 3.3 V 32-bit edge-triggered D-type flip-flop; 3-state
Product specification 2002 Mar 20
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop; 3-state
FEATURES * 32-bit edge-triggered flip-flop * 3-state buffers * Output capability: +64 mA/-32 mA * TTL input and output switching levels * Input and output interface capability to systems at 5 V supply * Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs * Live insertion/extraction permitted * Power-up reset * Power-up 3-state * No bus current loading when output is tied to 5 V bus * Latch-up protection exceeds 500 mA in accordance with JEDEC std 17 * ESD protection exceeds 2000 V in accordance with MIL STD 883 method 3015 and 200 V in accordance with Machine Model. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH CI CO ICCZ PARAMETER propagation delay nCP to nQn input capacitance output capacitance total supply current CONDITIONS CL = 50 pF; VCC = 3.3 V VI = 0 or 3.0 V outputs disabled; VO = 0 or 3.0 V output disabled; VCC = 3.6 V DESCRIPTION
74LVT32374
The 74LVT32374 is a high-performance BICMOS product designed for VCC operation at 3.3 V. The 74LVT32374 is a 32-bit edge-triggered D-type flip-flop featuring non-inverting 3-state outputs. The device can be used as four 8-bit flip-flops, or two 16-bit flip-flops or one 32-bit flip-flop. On the positive transition of the clock (CP), the Q outputs of the flip-flop take on the logic levels set-up at the D inputs.
TYPICAL 2.9 3 9 140 ns pF pF A
UNIT
2002 Mar 20
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Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop; 3-state
FUNCTION TABLE See note 1. INPUTS OPERATING MODE nOE Load and read register Hold Disable outputs L L L
M
74LVT32374
nCP
nDn l h X X
INTERNAL REGISTER L H NC NC
OUTPUTS nQn L H NC Z
H
H Note 1. H = HIGH voltage level;
nDn
nDn
Z
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW OE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW OE transition; NC = not connected; X = don't care; Z = high-impedance OFF-state; = LOW-to-HIGH CP transition; = not a LOW-to-HIGH CP transition.
ORDERING INFORMATION TYPE NUMBER 74LVT32374EC PINNING SYMBOL nDn nCP nQn GND nOE VCC data input clock input flip-flop output ground (0 V) output enable input (active LOW) supply voltage DESCRIPTION TEMPERATURE RANGE -40 to +125 C PACKAGE PINS 96 PACKAGE LFBGA96 MATERIAL plastic CODE SOT536-1
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Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop; 3-state
74LVT32374
handbook, full pagewidth
MNA497
6 5 4 3 2 1
1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D7 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D6 1D0 1D2 1D4 1D6 2D0 2D2 2D4 2D6 3D0 3D2 3D4 3D6 4D0 4D2 4D4 4D7 1CP GND VCC GND GND VCC GND 2CP 3CP GND VCC GND GND VCC GND 4CP 1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE 1Q0 1Q2 1Q4 1Q6 2Q0 2Q2 2Q4 2Q6 3Q0 3Q2 3Q4 3Q6 4Q0 4Q2 4Q4 4Q7 1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q7 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q6 A B C D E F G H J K L M N P R T
Fig.1 Pin configuration.
handbook, full pagewidth
1D0
D CP FF 1
Q
1Q0
2D0
D CP FF 9
Q
2Q0
1CP 1OE to 7 other channels
2CP 2OE to 7 other channels
3D0
D CP
Q
3Q0
4D0
D CP
Q
4Q0
FF 17
FF 25
3CP 3OE to 7 other channels
4CP 4OE to 7 other channels
MNA498
Fig.2 Logic symbol.
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Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop; 3-state
74LVT32374
handbook, halfpage
VCC
handbook, halfpage
VCC
27 output 27
data input
to internal circuit
MNA473
MNA676
Fig.3 Schematic of each output.
Fig.4 Bus hold circuit.
RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VIH VIL IOH IOL t/V Tamb PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 70 C the value of PD derates linearly with 1.8 mW/K. PARAMETER supply voltage input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current current duty cycle 50%; f 1 kHz input transition rise or fall times operating ambient temperature power dissipation per package note 2 outputs enabled note 1 CONDITIONS 0 2.0 - - - - - -40 - MIN. -2.7 MAX. +3.6 5.5 - 0.8 -32 32 64 10 +125 - V V V V mA mA mA ns/V C mW UNIT
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Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop; 3-state
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); note 1. SYMBOL VCC IIK VI IOK VO IO Tstg Notes PARAMETER supply voltage input diode current input voltage output diode current output voltage output current storage temperature output in LOW state output in HIGH state VI < 0 note 2 CONDITIONS - -0.5 - output in OFF or HIGH state; note 2 -0.5 - - -65 MIN. -0.5 - -50 - -50 - 128 -64 - TYP.
74LVT32374
MAX. +4.6 - +7.0 - +7.0 - - +150
UNIT V mA V mA V mA mA C
1. The performance capability of a high-performance integrated circuit in conjuction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. 2. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
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Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop; 3-state
DC CHARACTERISTICS Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIK VOH VOL VRST II input clamp voltage HIGH-level output voltage LOW-level output voltage power-up output LOW voltage input leakage current IIK = -18 mA IOH = -32 mA IOL = 64 mA IO = -1 mA; VI = GND or VCC; note 2 VI = VCC or GND; control pins VI = 5.5 V VI = VCC; data pins; note 3 VI = 0 V; data pins; note 3 Ioff Ihold output OFF current bus hold current D inputs VI or VO = 0 to 4.5 V VI = 0.8 V; note 4 VI = 2.0 V; note 4 VCC = 3.6 V; note 4 IEX Ipu/pd current into an output in the HIGH state when VO > VCC power-up/down 3-state output current VO = 5.5 V VO = 5.5 V to VCC; VI = GND or VCC; VOE = don't care; note 5 VO = 0.5 V; VI = VIH or VIL outputs HIGH; IO = 0; VI = GND or VCC outputs LOW; IO = 0; VI = GND or VCC outputs disabled; IO = 0; VI = GND or VCC; note 6 VCC (V) 2.7 3.0 3.0 3.6 3.6 0 or 3.6 3.6 3.6 0 3.0 3.0 0 to 3.6 3.0 1.2 V MIN. - 2.0 - - - - - - - 75 -75 500 - -
74LVT32374
Tamb (C) -40 to +85 TYP.(1) -0.85 2.3 0.4 0.1 0.1 0.4 0.1 -0.4 0.1 135 -135 - 50 1 MAX. -1.2 - 0.55 0.55 1 10 1 -5 100 - - - 125 100 V V V V A A A A A A A A A A UNIT
IOZH IOZL ICCH ICCL ICCZ ICC Notes
3-state output HIGH current VO = 3.0 V; VI = VIH or VIL 3-state output LOW current quiescent supply current quiescent supply current quiescent supply current additional supply current per input pin
3.6 3.6 3.6 3.6 3.6
- - - - -
0.5 +0.5 0.14 8 0.14 0.1
5 -5 0.24 12 0.24 0.2
A A mA mA mA A
one input at VCC - 0.6 V; other 3.0 to 3.6 - inputs at GND or VCC; note 7
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 2. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 3. Unused pins at VCC or GND. 4. This is the bus hold overdrive current required to force the input to the opposite logic state. 5. This parameter is valid for any VCC between 0 and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 0.3 V a transition time of 100 s is permitted. This parameter is valid for Tamb = 25 C only. 6. ICCZ is measured with outputs pulled to VCC or GND. 7. This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
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Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop; 3-state
AC CHARACTERISTICS GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; RL = 500 . SYMBOL tPLH/tPHL tPZH/tPZL tPHZ/tPLZ fmax Note 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 C. AC SETUP REQUIREMENTS GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 ; Tamb = -40 to +125 C. SYMBOL tsuH tsuL thH thL tWH tWL PARAMETER set-up time nDn HIGH to nCP set-up time nDn LOW to nCP hold time nDn HIGH to nCP hold time nDn LOW to nCP nCP HIGH pulse width nCP LOW pulse width WAVEFORMS see Fig.6 see Fig.6 see Fig.6 see Fig.6 see Fig.6 see Fig.6 VCC = 3.3 0.3 V MIN. 2.5 2.5 0.5 0.5 1.5 3.0 TYP.(1) 0.7 0.7 0 0 0.6 1.6 PARAMETER propagation delay nCP to nQn output enable time to HIGH and LOW level output disable time from HIGH and LOW level maximum clock pulse frequency WAVEFORMS MIN. see Fig.5 see Figs 7 and 8 see Figs 7 and 8 see Fig.5 1.5 1.5 1.5 1.5 1.5 1.5 150 VCC = 3.3 0.3 V TYP.(1) 3.0 3.0 3.5 3.2 3.5 3.2 - MAX. 5.3 4.9 5.6 4.9 5.4 5.0 -
74LVT32374
VCC = 2.7 V MAX. 6.2 5.1 6.9 6.0 5.7 5.1 -
UNIT ns ns ns ns ns ns MHz
VCC = 2.7 V MIN. 2.5 2.5 0 0 1.5 3.0
UNIT ns ns ns ns ns ns
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Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop; 3-state
AC WAVEFORMS
74LVT32374
handbook, full pagewidth
1/fmax 2.7 V nCP input 0V t PHL VOH nQn output VOL VM
MNA677
VM
VM
t PLH
VM = 1.5 V; VM = GND to 3.0 V.
Fig.5
Clock (nCP) to output (nQn) propagation delays, the clock pulse width and the maximum clock pulse frequency.
handbook, full pagewidth
2.7 V nDn input 0V t hH t suH 2.7 V nCP input 0V t WH t WL
MNA678
VM
t hL t suL
VM
The shades areas indicate when the input is permitted to change for predicable output performance.
Fig.6 Set-up and hold times for inputs (nDn) to inputs (nCP).
2002 Mar 20
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Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop; 3-state
74LVT32374
handbook, full pagewidth
2.7 V nOE input 0V t PZH VOH nQn output 0V
MNA679
VM
VM
t PHZ VOH - 0.3 V
VM
Fig.7 3-state output enable time to HIGH level and output disable time from HIGH level.
handbook, full pagewidth
2.7 V nOE input 0V t PZH 3V nQn output VOH VM VOL + 0.3 V
MNA680
VM
VM
t PHZ
Fig.8 3-state output enable time to LOW level and output disable time from LOW level.
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Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop; 3-state
74LVT32374
handbook, full pagewidth
VCC PULSE GENERATOR VIN D.U.T. RT CL RL VOUT RL
6V open GND
MNA681
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 6V
S1 open GND
Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.9 Load circuitry for switching times.
handbook, full pagewidth
tW AMP (V) negative pulse 0V tf tr AMP (V) positive pulse 0V 10% tW 90% VM 90% VM 10%
MNA682
90% VM 10% VM 10% tf tr
90%
INPUT PULSE REQUIREMENTS FAMILY AMPLITUDE 74LVT32xxx 2.7 V PULSE RATE 10 MHz tW 500 ns tr 2.5 ns tf 2.5 ns
Fig.10 Input pulse definition.
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Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop; 3-state
74LVT32374
PACKAGE OUTLINE LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
D
B
A
ball A1 index area
A E
A2 A1 detail X
e1 e T R P N M L K J H G F E D C B A 123456 b
vMB
w M
C y1 C y
vMA
e
e2
X
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.41 0.31 A2 1.2 0.9 b 0.51 0.41 D 5.6 5.4 E 13.6 13.4 e 0.8 e1 4.0 e2 12.0 v 0.15 w 0.1 y 0.1 y1 0.2 0 5 scale 10 mm
OUTLINE VERSION SOT536-1
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 99-12-02 00-03-04
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Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop; 3-state
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
74LVT32374
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2002 Mar 20
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Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop; 3-state
Suitability of surface mount IC packages for wave and reflow soldering methods
74LVT32374
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
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Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop; 3-state
DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
74LVT32374
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/01/pp16
Date of release: 2002
Mar 20
Document order number:
9397 750 08898

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